Circuits implemented with thin-film transistors (TFT) have been gaining in popularity over the last few years. It is thought that this is mainly due to an increase in performance presented by circuits implemented with TFTs and also a growing field of applications such as low-cost RFID/NFC tags, integrated scan drivers for displays and biomedical patches. Many thin-film circuits, such as tags and scan drivers, rely heavily on digital circuit blocks.
However, the digital blocks present in designs today can suffer from large power consumption as a consequence of the unipolar nature of some thin-film transistor technologies, such as metal-oxides or organics. Providing circuits with lower power consumption can enhance battery life for mobile devices and displays and enable increased complexity of RFID tags, etc.
One reason for the current high power consumption is the absence of complementary thin-film devices. The extra layer masks needed for producing complementary devices increase the manufacturing cost of the circuits. In addition, some technologies lack matching complementary alternatives of the semiconductor limiting the realization of complementary logic. One focus in the field is to find alternative circuit configurations based on unipolar technologies, mainly focusing on increased robustness and speed compared to diode-load or zero-VGS-load logic.
T. C. Huang et al., “Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics”, IEEE Transactions on Electron Devices, vol. 58, no. 1, pp. 141-150, January 2011 discloses the use of pseudo CMOS. This topology provides improved robustness and speed and is implemented with four TFTs to realize an inverter compared to a regular 2-TFT inverter. The drawbacks are still a high power consumption and the necessity to have two supply voltages and a ground connection (VDD and VBIAS or VSS).
K. Myny et al., “Robust digital design in organic electronics by dual-gate technology”, 2010 IEEE International Solid-State Circuits Conference—(ISSCC), San Francisco, Calif., 2010, pp. 140-141 discloses to improve diode-load logic by adding a backgate to increase its robustness. Dual-gate diode-load logic reduces chip area compared to pseudo-CMOS logic, but the power consumption is still large due to the on-state of the load transistor when outputting a logic zero.
J. S. Kim et al., “Dynamic Logic Circuits Using a-IGZO TFTs,” IEEE Transactions on Electron Devices, vol. 64, no. 10, pp. 4123-4130, October 2017 discloses the use of dynamic logic, which increases the speed and reduces size, but at the cost of high sensitivity to threshold voltage and timing, and requiring complex clock distribution systems.
M. Venturelli et al., “Unipolar Differential Logic for Large-Scale Integration of Flexible aIGZO Circuits”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 5, pp. 565-569, May 2017 discloses the use of differential logic for high static noise margin, but at the cost of no less than eight transistors per inverter, and as such chip area.
N. P. Papadopoulos et al., “Low-Power Bootstrapped Rail-to-Rail Logic Gates for Thin-Film Applications,” Journal of Display Technology, vol. 12, no. 12, pp. 1539-1546, December 2016 discloses a bootstrapped inverter with low power consumption, but this topology also uses five transistors per inverter.